Samsung Galaxy A10s (SM-A107) Power Architecture Explained
The Samsung Galaxy A10s (model SM-A107) is powered by a Mediatek architecture consisting of the MT6762 SoC and MT6357 PMIC. Power distribution in this smartphone is meticulously managed across various rails to support the CPU, RAM, eMMC, and other components. In this article, we’ll break down the power design using the schematic image below.
🔋 Battery & Main Supply
- Battery Voltage (BAT): 3.7V (nominal)
- VSYS: This is the main system power rail that comes from the battery through a protection and monitoring circuit.
VSYS powers the MT6357 PMIC, which is responsible for regulating and distributing various voltages required by the system.
⚙️ MT6357 PMIC (Power Management IC)
The MT6357 is the central power controller IC. It takes input from VSYS (3.7V) and generates several key voltages:
Key Outputs from PMIC:
- VIO18 (1.8V): Supplies SoC and eMMC I/O
- VDRAM (1.24V): Dedicated voltage rail for DRAM operation
- VEMC (3.0V): Supplies power to the eMMC storage
- VS1 (2.0V): General system rail
- VA12 (1.2V): Analog and PLLs via external LDO
🧠 SoC (MT6762 - Helio P22)
The main application processor is MT6762. It requires multiple low voltage rails:
- VPROC (0.8V): Core voltage for the CPU
- VCORE (0.8V): Internal processing units
- VMODEM (0.8V): For modem section
- VSRAM (0.75V - 0.8V): Voltage for SRAM blocks
- VUSB (3.0V): USB interface support
- VRTC (2.8V): Real-time clock and always-on sections
These rails are derived using internal buck converters from MT6357. Their exact values are carefully tuned to balance performance and power efficiency.
🧠 DRAM Power
The RAM (DRAM) has dedicated voltages:
- VDD1 / VDD2: 1.24V - DRAM core supply
- VDDQ: 1.24V - DRAM I/O voltage
- VDDCA: 1.24V - DRAM internal controller voltage
These are powered directly from VDRAM provided by the PMIC.
💾 eMMC (Embedded Storage)
- VCC: 3.0V - Core power for eMMC
- VCCQ: 1.8V - I/O voltage for communication with SoC
This setup ensures compatibility with high-speed eMMC standards while keeping power consumption optimized.
🔄 LDO (Low Dropout Regulator) & External Regulation
Some voltages are generated using external regulators:
- U1401 (Switching Regulator): Takes VSYS (3.7V) and generates 1.35V (VS2)
- U1402 (LDO): Takes VS2 (1.35V) and outputs VA12 (1.2V)
The 1.2V VA12 rail powers certain analog blocks and ensures clean power for sensitive components like PLLs or RF sections.
📌 Summary of Voltage Rails
| Voltage | Source | Destination / Function |
|---|---|---|
| 3.7V | Battery | Main input to PMIC (VSYS) |
| 3.0V | PMIC | eMMC (VCC), USB, VEMC |
| 2.8V | PMIC | RTC, always-on logic |
| 2.2V | PMIC | General-purpose I/O |
| 2.0V | VS1 | General system use |
| 1.8V | VIO18 | SoC I/O, eMMC I/O |
| 1.35V | VS2 | Input for LDO to make 1.2V |
| 1.24V | VDRAM | DRAM core, I/O, and controller |
| 1.2V | VA12 (LDO) | Analog, PLLs, RF sections |
| 0.8V | VPROC / VCORE | CPU, MODEM, SRAM |
| 0.75V | VSRAM | SRAM power rail |
📝 Final Thoughts
The power architecture of the Samsung Galaxy A10s, using the Mediatek MT6357 PMIC and MT6762 SoC, is highly optimized for mobile performance. Each voltage rail is precisely regulated to meet the needs of high-speed processing, memory performance, and power efficiency. Understanding this distribution is crucial for mobile repair engineers, reverse engineering, and anyone interested in SoC-level hardware design.
If you're troubleshooting the board, always measure these voltages at their respective capacitors or test points to identify dead rails or shorted components.
Image Source: Internal schematic of SM-A107 (MT6357 + MT6762)